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Hi,
There many things that need to be aligned. The very basic question is how does the FPGA logic gets laid out if your design. if there is only one interface given to the DMA, or only one interface implemented for register/memory access. I don't see how simultaneous concurrent accesses can happen, without diving into the complexity of SW layer above.
Thanks,
Chen
beantwortet vor 7 Monaten
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Thank you @Chen