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Hi,
The AppPF BAR2 maps directly to the 64KiB of address space for registers inside the XDMA IP.
This address space exposes the registers described in "PCIe to DMA (BAR1) Address Map" section in PG195 (https://www.xilinx.com/support/documentation/ip_documentation/xdma/v4_0/pg195-pcie-dma.pdf) user guide.
Hope this helps. Please contact us if you need anything else.
Thanks!
Chakra
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