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Hello,
Please refer to:
https://github.com/aws/aws-fpga/blob/master/hdk/docs/dynamic_clock_config.md
For details on finer control of the Shell sourced clocks. Also note the interfaces to the Shell are synchronous to clk_main_a0, so if you generate your own clock in the CL, you must synchronize the interfaces to the Shell to clk_main_a0. This may be the cause of your timing violations.
Thanks,
-Asif
Thanks, but I already know that document. The most important statement being "This will still not permit any clock value to rise above its ingested value.". I get violations as soon as my clock cannot be generated by multiplying the shell clock with an even number. So while 250 MHz does work, 225 MHz and 275 Mhz both do not work. And I cannot reach 275 MHz when building with 250 MHz.
Please see this screenshot:
http://img.ober-mail.de/2019-06-08_17-24-33-8c9613ad-fcb1-44b4-b658-d2fca9fa4425.png
I know communication with the shell must be sync to clk_main_a0. I'm using AXI Interconnects to ensure this. But as you can see, the timing violation is not from CDC.
clk_extra_b0 max frequency in the clock recipes is 450MHz. Does that give you the range you need with the configurable clock frequencies?
Thanks,
-Asif
I don't see yet how that would help me.
Let's say I have a given design. I now want to find the maximum frequency for it. Our toolchain starts multiple runs with different frequencies and finds the highest. It does so by changing the parameters of the MMCM and evaluating the timing report.
So you suppose I just use a 450 MHz clock for my design and build it without MMCM in the CL? Most likely this will result in timing violations. Ok, I can build an AFI anyway and load it. But now how do I know how far I have to downclock it?
What you can do is time the design at 450 and see what is your worst slack. Then you can back off the clock by that amount.
Thanks,
-Asif
Hi,
thanks for this suggestion, but I think this would not be feasible, because P&R stops after it determines the timing cannot be met. So the WNS is worse than it could possibly be. I found that for ISE there was an option to set the effort to "continue on impossible", which would try to find the best timing even if constraints cannot be met. It looks like there is no such setting for Vivado.
Nevertheless, it turned out the "Safe Clock Startup" setting of my clocking wizard was to blame for the timing failure, because this inserted another BUFGCE into the design. I have now disabled this option and can build my designs with all frequencies. Hopefully I will not run into other issues now.
Hi Miob,
I'm attempting to do something along these lines.
Once you generate a clocking wizard how do you point sdaccel to the IP? Right now I get a compile error that the IP is not found and I haven't figured out how to properly pull it into the build. Any help or pointers would be appreciated.
Thanks
Hi,
sorry, but I'm not using SDAccel - unfortunately I can't help you with this :(
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