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Bit stream generation failing due to MMCM instantiation

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I needed a phase-shifted (relative to the clk_main_a0) clock for my CL, and I implemented that using an MMCME4_ADV in my design. I ran into the well-known sub-optimal placement issues. When I did this in the pnr xdc: set_property CLOCK_DEDICATED_ROUTE ANY_CMT_COLUMN [get_nets WRAPPER_INST/SH/kernel_clks_i/clkwiz_sys_clk/inst/CLK_CORE_DRP_I/clk_inst/clk_out1] the checkpoint was generated but left my derived clock unrouted, leading to a failure in the AFI generation phase. What is the work around this? I have seen people posting this problem but none of them seemed to fail in the AFI generation stage. Thanks in Advaced

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FPGA 開発
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Fjaml
質問済み 9ヶ月前188ビュー
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Hi,

There could be multiple reasons for unrouted net. The most common ones are that the derived clock signal is by accident not connected properly or the the design is congested. Have you carefully looked through the build log and checked if there is any warning or critical warning for the clock signal or the MMCM? Also, have you tried a second time and it failed in the exactly same way?

Thanks,

Chen

AWS
AWS-zhcz
回答済み 9ヶ月前

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