XDMA register layout in BAR2 of AppPF
Hi There
I am looking for the next level of detail on how the XDMA registers are mapped into BAR2 of the AppPF in the AWS F1 shell. I know I could read the XDMA driver code and try and work it out from there but I was hoping there was documentation for this and I was missing it. Any pointers would be appreciated! I am looking for specific offsets in BAR2 and what XDMA registers they map too. I can then use the XDMA IP user guide to work out exactly what those registers can do.
Stephen
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Hi,
The AppPF BAR2 maps directly to the 64KiB of address space for registers inside the XDMA IP.
This address space exposes the registers described in "PCIe to DMA (BAR1) Address Map" section in PG195 (https://www.xilinx.com/support/documentation/ip_documentation/xdma/v4_0/pg195-pcie-dma.pdf) user guide.
Hope this helps. Please contact us if you need anything else.
Thanks!
Chakra
