ERROR: [Place 30-678] Failed to do clock region partitioning

Question

Hi,

Getting the following error while implementing my custom logic.

ERROR: [Place 30-678] Failed to do clock region partitioning: Cannot find an available clock routing track for clock net WRAPPER_INST/CL/cl_inst/*xyz*/BUFGCE_inst_0 in its partition defined by a rectangle from clock region X2Y11 to clock region X2Y13. A clock partition is a rectangular area covering all clock loads and the clock region for its clock root. It may cover the clock source as well. Each clock net needs to use the same routing track across all clock regions of its partition. In this case, other clock nets are already using resources in one or more clock regions of this partition.

Overall utilization is very less.

In few runs it is not showing this error and implementation completed successfully.

But in few runs, even without changing the design, the above error is thrown. Kindly help me solving this.

Thank you.

Accepted Answer

Hi @AWS-User-7905434

Thank you for the reply.

I tried placing all BUFGCEs manually as it is recommended [here](https://support.xilinx.com/s/article/67674?language=en_US)

I did not use any LOC constraint for the BUFGCE previously. Any how according to the second suggestion in the above link, I placed all the BUFGCEs manually using CLOCK_REGION constraint.

After this modification. The error is gone.

Answer

Please refer to https://github.com/aws/aws-fpga/issues/620 for guidance with the issue.

Thanks

Answer

Dear customer

Do you see this error only for a specific version of Vivado, or do you also see this issue with other tool versions? Also can you confirm if the clock net referred to is part of your CL design and if the constraint was added by your CL?

Thanks

ERROR: [Place 30-678] Failed to do clock region partitioning

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