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Hi @zqsteve
From the messaging, this should be related to a reported issue that is currently being worked on. The Vivado Error ID is missing, but the rest of the text looks to match. The reported issue was found to have boundary clock(s) between the static and dynamic regions, where there were no loads in the boundary that was crossed. A known workaround is to add loads to a load-less boundary clock.
How can I tell which clock lacks load? Then how can I add loads to the load-less boundary clock ?
I'm not sure that there is generalized Tcl that could be used for any design to find this. Are you able to open the netlist design within Vivado? If so, selecting the clock nets driving into and driving out of the dynamic region would help. The properties tab will show the number of number of loads as the FLAT_PIN_COUNT - 1, as one of the pins that is counted is the driver.
The loads can be added one one of two ways
-Through source files.
-Through netlist edits using ECO commands (https://www.xilinx.com/support/documentation/sw_manuals/xilinx2019_2/ug904-vivado-implementation.pdf#page=158)
Hi,
I had the same problem, perhaps this: https://forums.aws.amazon.com/message.jspa?messageID=944390#944390 can be useful to you as well.
Mikhail
I have also found that disabling phys_opt_design in the implementation flow can be used as a workaround. I would think this would be easier to test as well.
To clarify on the suggested workarounds for this issue, three suggestions are available.
1 Try to control the clock tracks usage using properties like CLOCK_LOW_FANOUT if the loads of the one of the clock nets are in the recommended range for CLOCK_LOW_FANOUT.
2 Disable the post placement's phys_opt_design step in the implementation proces if your WNS at post-placement is reasonably good.
3 If you are observing the issue only in second implementation in the DFX flow, Keep all these clocks in design in the first implementation itself, so that first implementation in the DFX flow (where the static region is implemented and locked down) is run in the context of all clocks in the design.
Adding the answer record with the above suggestions.