DDR performance drop with specific address access pattern


Hi, we are seeing performance drop when we access specific address pattern from DDR. Please find the below details.

in a single test we read same address repeatedly as mentioned below

rd_addr is 64B aligned and each read transaction is rd_len=1 (128B access)

'P' is the expected performance number

rd_addr =

0 -> no drop (P)

2 -> no drop (P)

4 -> drop (~P/4)

6 -> drop (~P/4)

8 -> no drop (P)

10 -> no drop (P)

12 -> drop (~P/4)

14 -> drop (~P/4)

..........this pattern repeats........

following are the results if we read more than 1 address repeatedly

{0, 2} -> no drop (P)

{4, 6} -> drop (~P/2)

{2, 4} -> drop (~P/2)

{0, 2, 4, 6} -> no drop (P)

{8 ,10} -> no drop (P)

{4 , 12} -> drop (~P/2)

{4, 6, 8, 10} -> no drop (P)

{4 ,6 ,12, 14} -> no drop (P)

is there any known DDR performance limitation for the above address pattern?



asked 7 months ago230 views
1 Answer


The DDR Controllers in F1 are configured to maximize the performance for incremental/sequential address patterns using the "ROW_COLUMN_BANK_INTLV" addressing mode and "Force Read and Write commands to use AutoPrecharge" option enabled in the IP. When these options are selected, the Memory Controller issues a transaction to memory with an AutoPrecharge if Column address bit A3 is set High. Please see PG150 for details on this configuration. Apparently, Column Address bit A3 corresponds to AXI4_Address bit[8].

If the user access patterns are to the same addresses (non-incremental pattern) then it is possible that the controller auto closes the current Bank/Row after a transaction but incurs penalty of re-opening the same bank/row and hence resulting in poor performance.

Please let us know if you have any questions.

Thanks! Chakra

answered 6 months ago

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