Custom Clock Recipe

Hi Sai,

Thank you for reaching for out for the clock question you have. We don't support arbitrary clock frequencies via the clock recipe. However, you can consider using one of the shell clocks to drive a local MMCM in the CL, that could be helpful to get you a output clock frequency you want or close enough. Hope this helps!

Regards,

Chen

I tried doing this but it complained about MMCM violating some location in the FPGA. Has this been tried ever?

Regards,

Hi Sai,

Yes, we know there are customers instantiating MMCM in CL. Can you please provide the violation error?

Thanks,

Chen

I get the following error. I dont get this error if I dont have the MMCM instantiated.

ERROR: [DRC HDPR-25] Reconfigurable Pblocks must not overlap same frame: Reconfigurable Pblocks cannot share a column within a Clock Region. Reconfigurable cell 'WRAPPER_INST/CL' in Pblock 'pblock_CL' and reconfigurable cell 'WRAPPER_INST/SH' in Pblock 'pblock_SH' violate this rule. The following are 10 of the tiles that are causing overlaps: INT_X0Y899 CLEL_R_X0Y899 CLEM_X1Y899 INT_X1Y899 INT_INTF_R_X1Y899 CLEM_X2Y899 INT_X2Y899 CLEL_R_X2Y899 CLEM_X3Y899 INT_X3Y899