DDR usage in f1 FPGA Instance

Hello,

F1 has four 16GB DDRs so you may choose to save your data in any (or all) the DDRs. The description of DDR/DRAM interface can be found in the AWS_Shell_Interface_Specification.md#ddr4-dram

You will need SH_DDR instantiated in the op level CL as shown in our example design cl_dram_dma.sv#L535-L666. Please note that SH_DDR has 512-bit AXI4 interface.

If you need 64-bit data stream continuously from DDR then your datapath logic should be capable of issuing AXI4 Write/Read requests, and perform AXI4-to-Stream conversion. There are IPs available in Vivado IP Catalog to perform AXI4-to-AXIS conversion and width conversions. An example datapath would be as shown below:

{Customer Logic} --> AXI4-Read Request --> [SH_DDR]

{Customer Logic}<-- Convert to Streaming interface <-- AXI4-Read Response <-- [SH_DDR]

https://www.xilinx.com/products/intellectual-property/axi_fifo.html#overview

Please let us know if you have any questions.

Thanks! Chakra