questions for F1 during STA

Question

Hello.

I have a few of questions during checking STA for implementing FPGA design for F1 instance.

During STA, there are some violation points that I cannot understand. I uploaded a image to give you an example start-end points.

this example points violate hold timing.

the start point of FF updates data at rising of clock DRCK ( @ 3.125Mhz),

and the destination point updates data at rising of clock TCK. (@ 3.125Mhz).

I think if those two FF has synchronous relationship, the clock relationship should be defined as same clock groups.

But my timing reports indicate that those two clock groups are defined as **inter-clock** relationship. (I think this causes high hold slack during implementation)

Could you please explain me for this case? (which means can I set those clocks as same clock groups by myself)

thanks

Steven.

![Timg report](/media/postImages/original/IMcKGjXkW1SSuRhPzkOPyx2A)

Accepted Answer

Hello,

Thank you for reaching out on this topic. We have reviewed the timing path and confirm the following:

•	The timing path shown between Source and Destination is a real path and should not be treated as a CDC false_path or multi_cycle_path.

•	The destination clock is created by the debug_bridge_0 IP’s constraints and needs to be timed with the source clock as reported in the timing path. Since the clock divider circuit is being generated through logic, a create_generated_clock constraint is being made in the IP.

•	The hold violation is fixed by the tool during routing but not during placement. It is possible that the vivado tool compromises on TNS in order to fix the hold violations. Therefore, we strongly recommend doing hold timing analysis based on a routed DCP.

•	If the design fails to close timing (setup or hold) in post route, we recommend running placement/route using multiple directives and/or reduce design congestion. Also, phys_opt_design has switches to assist with hold timing when necessary.

Please reach out to us if you have any additional questions.

Thanks!

Chakra

Answer

Hello Chakra.
Thank you for your deep analysis for shown violation path and your kind response for my question.
I have one more question.

**Since the clock divider circuit is being generated through logic, a create_generated_clock constraint is being made in the IP.**
        
I agreed with your opinion and the violation path is always resolved by a tool after post route step.
I would like to ask you if each output of each FF meets drived by each clock(free running clock and divided clock) each other, how should we consider the clock relationship between those clocks.
Because I thought the relationship between a clock (create_clock) and another clock(create_generated_clock) should be synchronous. -->Do we need to define it as sync? (set_clock_groups -async -clock {drck tcl} ... )

Thank you
steven

Answer

Hello, thank you for reaching us on this topic. Would you be able to share the full timing report for the violating path?

Thanks!
Chakra

Answer

Hello Steven,

Thank you for sharing timing report, as we only need the timing path between the following Source/Destination:

```
Slack (VIOLATED) :        -0.939ns  (arrival time - required time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_EXT_BSCAN.bscan_switch/state_reg[2]/C
                            (rising edge-triggered cell FDRE clocked by drck  {rise@0.000ns fall@16.000ns period=32.000ns})
  Destination:            WRAPPER_INST/CL/debug_bridge_0/inst/xsdbm/inst/BSCANID.u_xsdbm_id/EXT_BSCAN.id_state_reg[1]/D
                            (rising edge-triggered cell FDRE clocked by tck  {rise@0.000ns fall@16.000ns period=32.000ns})
```
One more question -- could you also confirm if you are using AWS provided [cl_debug_bridge.xci](https://github.com/aws/aws-fpga/blob/master/hdk/common/shell_v04261818/design/ip/cl_debug_bridge/cl_debug_bridge.veo) for the `WRAPPER_INST/CL/debug_bridge_0/` instantiation, and followed guidelines described in the following link?

https://github.com/aws/aws-fpga/blob/master/hdk/docs/Virtual_JTAG_XVC.md#embedding-debug-cores-in-the-cl

We will continue investigating this issue on our end and keep you posted.

Thanks!

Chakra

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