Inserting ILA is improving the performance

0

Hi,

Enter image description here

Look at the above image. From module A, a gated clock is going to module B. We found that module B is not functioning properly. So, inserted ILA 1 in **module B ** and found that gated clock is always high inside module B. To identify the root cause, we inserted ILA 2 in module A. After inserting the ILA 2 in module A, both modules are functioning as expected. And when we removed the ILA 2 from module A, again the same problem faced in module B.

What will be the cause of this issue? NOTE: We are using BUFGMUX (to replace OR gate) for gated clock.

Thank you.

GOGUL
asked 5 months ago169 views
1 Answer
0

Hello!

This appears to be a duplicate of an open GitHub issue: https://github.com/aws/aws-fpga/issues/629

answered 5 months ago

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