DMA read is not correct

Hi @Chen,

Thank you for your answer. I think the problem is sorted out. While customizing the Block Memory Generator in Vivado, Under the category Optional Output Registers in Port options, Primitive Output Register was enabled. When it was enabled, it is automatically taking the latency of 2 clock cycles. I have disabled it so that the latency becomes 1 clock cycle. This is the first modification I have done.

And I observed that the files in the following path was missing. aws-fpga/hdk/common/shell_v04261818/design/ip/axi_register_slice.

Actually it is in the repo. I don't know how the files got deleted from this folder. I have replaced the files in that folder.

Both modifications I have done with the help of your first comment. I don't know which modification helped to resolve the error.

Thank you so much.

Hi @Chen

This is what my exact design.

bram_gen_adc_1_1 is a BRAM of 1 MB. I am trying to read from the BRAM using DMA. It is a True Dual Port BRAM. BRAM is written using PORT B by my design and I have to read and verify using PORT A. Read Latency is set as 2 for both BRAM Controller and BRAM Memory. Reading and Writing is not happening parallelly. After writing into BRAM there is an interrupt generated. After the generation of the interrupt only I am trying to read it.

Thank you

Hi @GOGUL,

Thanks for sharing the block diagram. I recommend adding ILA or system ILA cores to both the write and read AXI buses around the BRAM IP. That can help rule out whether the rdata duplication is truly happening in HW/RTL.

Thanks,

Chen