DMA read is not correct

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Hi,

I was trying to read a memory from FPGA using DMA read and I got the following output. a4, e, 25, 3c, 28, 85, dc, 5, a4, e, 25, 3c, 28, 85, dc, 5.

8 bytes are repeated here. The expected output is a4, e, 25, 3c, 28, 85, dc, 5, e6, 57, 45, 88, 9d, 73, a5, a7.

I have to read twice to get the proper output. If I read the entire memory using PCIe, I am getting the correct data. What is the cause of this problem.?

Even while using PCIe, I am facing this problem sometimes. So that I have to read twice to overcome this. But due to timing constraint I have to read only once.

Kindly help me.

Thank you.

GOGUL
asked 6 months ago217 views
4 Answers
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Accepted Answer

Hi @GOGUL,

Without exposing to all the details of the design, it'll be extremely difficult to diagnose this type of issue. Here is just a quick thought based upon the symptom you described. Is there any FIFO or register slice on this data path? I'm wondering if the FIFO read data valid flag was accidentally ignored or the read latency wasn't set correctly so the downstream logic actually sampled an outdated/stale data before the real one gets popped from the FIFO?

Chen

AWS
answered 6 months ago
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Hi @Chen,

Thank you for your answer. I think the problem is sorted out. While customizing the Block Memory Generator in Vivado, Under the category Optional Output Registers in Port options, Primitive Output Register was enabled. When it was enabled, it is automatically taking the latency of 2 clock cycles. I have disabled it so that the latency becomes 1 clock cycle. This is the first modification I have done.

And I observed that the files in the following path was missing. aws-fpga/hdk/common/shell_v04261818/design/ip/axi_register_slice.

Actually it is in the repo. I don't know how the files got deleted from this folder. I have replaced the files in that folder.

Both modifications I have done with the help of your first comment. I don't know which modification helped to resolve the error.

Thank you so much.

GOGUL
answered 6 months ago
  • Glad to hear that the problem has been resolved. You're welcome.

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Hi @Chen

This is what my exact design.

bram_gen_adc_1_1 is a BRAM of 1 MB. I am trying to read from the BRAM using DMA. It is a True Dual Port BRAM. BRAM is written using PORT B by my design and I have to read and verify using PORT A. Read Latency is set as 2 for both BRAM Controller and BRAM Memory. Reading and Writing is not happening parallelly. After writing into BRAM there is an interrupt generated. After the generation of the interrupt only I am trying to read it.

Thank you

GOGUL
answered 6 months ago
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Hi @GOGUL,

Thanks for sharing the block diagram. I recommend adding ILA or system ILA cores to both the write and read AXI buses around the BRAM IP. That can help rule out whether the rdata duplication is truly happening in HW/RTL.

Thanks,

Chen

AWS
answered 6 months ago

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