Questions tagged with FPGA Development

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Hi everyone, Is it possible to run Vitis in GUI mode in AWS f1 instance through remote desktop? I have created AFI using Vivado. Can I test it using Vitis GUI? Kindly help me. Thank you.
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GOGUL
asked 3 days ago
Hi everyone, While doing synthesis for creating AFI using vivado IPI , I get this error. **ERROR: [Common 17-107] Cannot change read-only property 'is_locked'.** Resolution: Please refer to Vivado Properties Reference Guide (UG912) for more information on setting properties. Please help me solving this. Thank you.
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GOGUL
asked 3 days ago
hi, I am new at AWS and at f1 instance. I connected to f1 instance and to remote desktop but I cant understand how to go further from that point. What I want to ask is 1) Do you know any good tutorials how to use f1 instance and develop in vitis? I found many tutorials but they seems to be very general. 2) If I would like to develop on my computer and only run the hardware on AWS f1, what platform should I use? Thanks allot
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roman
asked a month ago
Hello. I have a few of questions during checking STA for implementing FPGA design for F1 instance. During STA, there are some violation points that I cannot understand. I uploaded a image to give you an example start-end points. this example points violate hold timing. the start point of FF updates data at rising of clock DRCK ( @ 3.125Mhz), and the destination point updates data at rising of clock TCK. (@ 3.125Mhz). I think if those two FF has synchronous relationship, the clock relationship should be defined as same clock groups. But my timing reports indicate that those two clock groups are defined as **inter-clock** relationship. (I think this causes high hold slack during implementation) Could you please explain me for this case? (which means can I set those clocks as same clock groups by myself) thanks Steven. ![Timg report](/media/postImages/original/IMcKGjXkW1SSuRhPzkOPyx2A)
Accepted AnswerFPGA Development
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50
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asked a month ago
Hello, Is there a way to create your own clock recipe instead of whats provided in https://github.com/aws/aws-fpga/blob/master/hdk/docs/clock_recipes.csv Say for example I want to create a 160 MHz clock. Is there a way to do this? Regards, Sai.
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asked 2 months ago
Hi, I am using the AWS F1 instance to create my own accelerator in CL portion. There are multiple blocks in my hierarchy and what I want to be able to do is assign a hierarchical block to my own pblock. You can generally create a pblock via the vivado gui. I opened the synthesized DCP and tried creating a pblock. When I try to save the constraints, it does not get saved anywhere. Is there a way I can do this or do I need to do this via XDC file only? Thanks.
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asked 2 months ago
Hello aws, depites of the aws support of https://repost.aws/questions/QUn-Z39lZhRaS_g93s0U32Eg/how-should-i-delete-afi-that-is-stuck-in-pending, AFI gen of my design with full functionality still has same issue -- the afi state is stuck in pending. ``` { "FpgaImages": [ { "FpgaImageId": "afi-0092bd7a65eb6908c", "FpgaImageGlobalId": "agfi-074215586b74cb0d4", "Name": "", "Description": "", "State": { "Code": "pending" }, "CreateTime": "2022-10-06T23:49:51+00:00", "UpdateTime": "2022-10-06T23:49:51+00:00", "OwnerId": "034954464192", "Tags": [], "Public": false, "DataRetentionSupport": false } ] } ``` Could you please abort the process to delete the AFI again? Moreover, I can provide the same xclbin file whose control-status registers are hacked not to be programmed. Could you please check out if my xclbin has some problem to be generated? https://drive.google.com/file/d/1Y_N6_aB0Ppm8iVLqqPBGAjCwhDO6-9I-/view?usp=sharing Thank you. Steen Kim
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asked 4 months ago
I'd like to share FPGA images with just accounts in my company's AWS organization. https://awscli.amazonaws.com/v2/documentation/api/latest/reference/ec2/modify-fpga-image-attribute.html suggests appending user-groups to user groups might work, but the [aws-fpga FAQ](https://github.com/aws/aws-fpga/blob/v1.4.23/FAQs.md). implies this can only be done a global scope. Is there any plan support user-defined groups, or should I share with a list of IDs?
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20
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asked 4 months ago
I'd created several AFIs that are all stuck in 'pending' from the end of Aug. the relative thread is https://repost.aws/questions/QU-CsdCyAqTxedKYkG9PuwtA/pending-create-fpga-images-using-aws-ec-2 when I've tried to delete all stuck AFIs and the commands was banned because of OperationNotPermitted. How can I delete the AFIs regardless of their states? Thank you.
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69
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asked 4 months ago
So I am using the AWS F1 instance with a modified CL_SDE example from the GIT repo. We modified the HDL in the example to allow us to invert the loopbacked data through a control register, stop the internal loopback, see the last packet in/out on the control registers, and to see the packet counters.... Something super simple but exercises a lot of our libraries... We run the testpmd tool and the packet counters we have matches the tool. We see that the testpmd tool sends in a 64 byte packet as expected and that seems to repeat. When I invert the data, the testpmd keeps reporting everything as loopbacking back just fine(no data integrity checking). When I stop the traffic via my control register, traffic stops. This all seems like the simple hardware does what I want and matches the sim we created. We are now moving over to use the DPDK pktgen tool to generate some more strenuous and controllable traffic. I was able to get the DPDK pktgen libary to compile (I had to use the same tag for the GIT repo as the DPDK version). It appears to have built and installed just fine. However, it doesn't run well. I have tried a number of things (devbind) and all sorts of things, but I keep getting a message saying "did not find any ports to use". In the Virtual ethernet example, the end to end example uses the PKTGEN tool to generate traffic and send it over an elastic network interface to another VM. I am just trying to get PKTGEN to talk directly to the FPGA. In the link below under end to end, I am just trying to get the PKTGEN tool to bind to the SPP directly. Has anyone been able to get the PKTGEN tool to work directly with the FPGA? https://github.com/aws/aws-fpga/blob/master/sdk/apps/virtual-ethernet/doc/Virtual_Ethernet_Application_Guide.md#HelloWorldLoopback I have tried a number of things, but to no avail on this. Copyright (c) <2010-2020>, Intel Corporation. All rights reserved. Powered by DPDK EAL: Detected 8 lcore(s) EAL: Detected 1 NUMA nodes EAL: Auto-detected process type: PRIMARY EAL: Multi-process socket /var/run/dpdk/pg/mp_socket EAL: Selected IOVA mode 'PA' EAL: No available hugepages reported in hugepages-1048576kB EAL: Probing VFIO support... EAL: No legacy callbacks, legacy socket not created *** Copyright (c) <2010-2020>, Intel Corporation. All rights reserved. *** Pktgen created by: Keith Wiles -- >>> Powered by DPDK <<< Port: Name IfIndex Alias NUMA PCI !PANIC!: *** Did not find any ports to use *** PANIC in pktgen_config_ports(): *** Did not find any ports to use *** 6: [veth_app/Pktgen-DPDK/Builddir/app/pktgen() [0x404baa]] 5: [/lib64/libc.so.6(__libc_start_main+0xea) [0x7ffa3d16013a]] 4: [veth_app/Pktgen-DPDK/Builddir/app/pktgen() [0x4047fd]] 3: [veth_app/Pktgen-DPDK/Builddir/app/pktgen() [0x42681b]] 2: [/usr/local/lib64/librte_eal.so.20.0(__rte_panic+0xba) [0x7ffa3db5aeaa]] 1: [/usr/local/lib64/librte_eal.so.20.0(rte_dump_stack+0x1b) [0x7ffa3db7a09b]] Aborted [ec2-user@ip-10-20-7-111 runtime]$
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21
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asked 5 months ago
Hi all.. I've tried to create aws-fpga-images with xclbin files generated by v++. the detailed situation I've met now is below, 1) created "awsxclbin files" using command "**aws ec2 create-fpga-images -xclbin={my_xclbin} -o={my_awsxclbin_name} -s3_bucket={my_bucket} -s3_dcp_key={my_dcp_repo} -s3_logs_key={my_log_repo}**" 2) all txt, json, and awsxclbin files were successfully generated in my local linux machine. 3) "**aws ec2 describe-fpga-images --fpga-image-ids {generated_afi_ids}**" showed the bitstream is pending (still pending) 4) opened aws ec2 website 4) I found that the .tar file generated by aws ec2 command exists in {my_dcp_repo} 5) I couldn't find the vivado log files in {my_log_repo} However, my request status for create-fpga-images is now still pending. (the request was created on Aug 25 2022). Can I find the detailed status of the ongoing request on aws websites?
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76
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asked 5 months ago
I noticed the latest developer AMI has 2022.1 installed, and would like to upgrade my fork of aws-fpga to use it (to workaround a Vivado bug). When will there be a cut of aws-fpga supporting that version?
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75
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asked 5 months ago