Questions tagged with FPGA Development
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Hi,
I have been running a simulation in Vivado.
Writing into the BRAM of 16 KB through PCIS is taking more than 2 hours.
I need to write more than 10 BRAMS. If it takes time like this, I am worrying...
Hi,
I have a text file. It has 32 bit data in each line up to 4096 lines.
My testbench needs to read the text file and loads a memory which is connected to SHELL's PCIS/DMA using the...
Hello, I am having an issue with a program running on an Amazon F1 FPGA instance.
When I run the program, the program gives me this error message when I run it with the environment variable...
Right now I'm working to put a MicroBlaze core with Vivado IP Integrator flow, however, I can't connect to the MicroBlaze Debug Module (MDM) when I deployed in on an EC2 F1 instance.
My design is as...
Can I use "host memory access" in Amazon F1 instance? Alveo supports such a feature that provides DMA bypass capability used for FPGA to transfer date to the host on a No-DMA platform. Since I have...
Hi,
Is it possible to upgrade the F1 nodes' Viti's version to 2023.2?
I am currently using the AMI 1.2 image.
To check AMI and AFI approved by others using AWS cli,
I used the command "aws ec2 description-fpga-images > output",
An error occurred (UnauthorizedOperation) when calling the DescribeFpgaImages...
hello,
on the F1 instances, is there a way to access the full 72 bit of the DDR4 banks from the CL?
our application would benefit from giving up ECC support, and having access to the extra bits in...
I am following the documentation linked below. I was able to build the image successfully but when I try to complete step 7 I get an error in the console also shown below. Since the script that runs...
I cannot pop up GUI when I use mobaxterm if I set emulation debug=gui in Amazon AMI here https://aws.amazon.com/marketplace/pp/prodview-hxbanceez6tso.
It should pop up if I set it when I do HW...
Hi,
Look at the above image. From **module A**, a gated clock is going to **module B**. We found that **module...
Hi,
I was trying to read a memory from FPGA using DMA read and I got the following output.
a4,
e,
25,
3c,
28,
85,
dc,
5,
**a4,
e,
25,
3c,
28,
85,
dc,
5**.
8 bytes are repeated here.
The expected...