Questions tagged with FPGA Development
Content language: English
Select up to 5 tags to filter
Sort by most recent
Browse through the questions and answers listed below or filter and sort to narrow down your results.
Is it possible to directly transfer data via p2p DMA from one of the NVMe SSDs to/from the FPGA?
In a non-cloud environment, it does work if your PCIe root complex / PLX switch supports...
1
answers
0
votes
309
views
asked 5 years agolg...
Hi,
can I assume that in the sh_cl_apppf_irq_ack interface, at most one bit is set? Or is it possible that in a single clock cycle multiple bits are set?
Let's say I send a request on...
Accepted AnswerFPGA Development
1
answers
0
votes
198
views
asked 5 years agolg...
Hello.
Is it possible to access the FPGA from multiple threads or processes ?
- Can I attach to the same FPGA from multiple processes at once?
- Can I open a DMA queue from two or more...
2
answers
0
votes
216
views
asked 5 years agolg...
Hi,
for our project, we have a toolchain that tries to find the optimal frequency for a design. It does so by configuring a Clocking Wizard, building a bitstream and then evaluate the timing...
9
answers
0
votes
394
views
asked 5 years agolg...
Hi ,
I am creating a project with a pblock drawn in SLR2 and when i implement it , I am getting the following errors in the place design stage :
ERROR: (DRC HDPR-6) Logic illegally placed: Cell...
6
answers
0
votes
461
views
asked 5 years agolg...
Hello.
I am trying to add an ILA to check the behavior of an AXI bus in my design.
My design works in simulation but gets stuck on the FPGA. In order to debug this I want to check an AXI bus...
6
answers
0
votes
288
views
asked 5 years agolg...
Hi,
I am about to build a new on-premises server, to develope with AWS HDK 1.4.8+ (2018.3) release, and wondering what is the recommended Linux OS version?.
What are the minimun system...
4
answers
0
votes
194
views
asked 5 years agolg...
Hi,
the Shell specification says:
> **This interface uses single clock pulses for the req/ack.** The CL asserts (active high) cl_sh_apppf_irq_req\[x] for a single clock to assert the interrupt...
1
answers
0
votes
355
views
asked 5 years agolg...
Hi,
I am simulating my design after connecting it to the DDRB, but ddrb_is_ready doesnt get asserted.
I am using the IPI flow. I have customized the F1 IP to enable DDRB interface and...
2
answers
0
votes
190
views
asked 5 years agolg...
Hello
I recently updated my on-premise development tools to 2018.2, and the rtl_kernel examples are failing with error against the gen_XXX.tcl script.
For example, for the following example:...
1
answers
0
votes
200
views
asked 5 years agolg...
Hi,
I'm trying to integrate the Shell into an existing project, which already makes heavy use of scripts to build the design. So I thought it might be easier to only pick the relevant pieces from...
Accepted AnswerFPGA Development
3
answers
0
votes
279
views
asked 5 years agolg...
Hi,
Is there example or tutorial for burst mode of AXI-4?
I am trying to use burst mode to write bulk data to DRAMs. Apart from burst signals on FPGAs, I did not find which c program or...
1
answers
0
votes
360
views
asked 5 years agolg...