Questions tagged with FPGA Development
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Hello,
I seem to have a design that is barely routable. I found that if I reduce the AXI master address width to 16 bits it routes (but does not function). At 64 bits it does not route.
I only...
1
answers
0
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224
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asked 5 years agolg...
My synthesis runs have been working fine until a recent set of innocuous modifications to the source. All of a sudden I'm getting errors in synthesis that have to do with an axi_register_slice I have...
4
answers
0
votes
253
views
asked 5 years agolg...
Hello,
I see there is a new feature in xocc to synthesize and implement and RTL kernel in Vivado and feed the result back into to the xocc flow (at least, that is how I understand it).
When I...
7
answers
0
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176
views
asked 5 years agolg...
While compiling my desing with the latest version of HDK Kit (HDK_VERSION=1.4.7) and Vivado version 2018.2, I get the following error.
ERROR: \[XSIM 43-3316] Signal SIGSEGV received.
I also...
1
answers
0
votes
788
views
asked 5 years agolg...
Hi,
I am setting up on-prim development tools for AWS FPGA development. I installed Centos7.6 and downloaded the AWS HDK Kit. Followed all the steps of sourcing the hdk_setup.sh and setting up...
3
answers
0
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225
views
asked 5 years agolg...
Installation of the **Xilinx Runtime** on a clear **Amazon Linux 2** instance (which is RedHat based) leads to OpenCL runtime errors.
**Xilinx Runtime (XRT) 2018.2_XDF.RC5** Installation...
2
answers
0
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283
views
asked 5 years agolg...
I am getting the following errors, while trying to simulate my design with AWS shell. It seems like the arch_package, proj_package declaration is missing. Where are they supposed to be declared. I...
1
answers
0
votes
253
views
asked 5 years agolg...
While running a build, I got the error "EXCEPTION_ACCESS_VIOLATION". I checked the log pointed to by the message and it was empty. I closed Vivado and restarted in a fresh directory. But this time,...
3
answers
0
votes
220
views
asked 5 years agolg...
Hi,
I am using the cl_sde example in my design, including its IPs.
I use vivado v2018.2_AR71275_op (included in FPGA Developer AMI v1.5.0).
The problem: I can't generate the included sde...
1
answers
0
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183
views
asked 5 years agolg...
Hi Amazon Team,
As requested in the previous thread:<https://forums.aws.amazon.com/thread.jspa?messageID=887224󘦸>
I am unable to source the hdk_setup script with maintaining the...
2
answers
0
votes
214
views
asked 5 years agolg...
Hello,
if I understand the architecture correctly, I can only have 16 interrupts \[1]. Is this correct? For my current project, it would be good to have 128+ interrupts. Is there any way to...
Accepted AnswerFPGA Development
3
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0
votes
199
views
asked 5 years agolg...
Hi,
Does anybody know how to get utilization and timing reports when using SDAccel + RTL flow?. I was trying to use **--report estimate** on **xocc** but it is not reporting anything on the...
2
answers
0
votes
194
views
asked 5 years agolg...