Questions tagged with FPGA Development
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XRT ERROR : failed to load xclbin : input output error hello_world tutorial on AWS F1 / AMI 1.12.2lg...
I encountered an error during the official tutorial. (https://github.com/aws/aws-fpga/blob/master/Vitis/README.md)
I followed the tutorial in
AWS F1(f1.2xlarge) instance / oregon
FPGA Developer AMI...
Accepted AnswerFPGA Development
3
answers
0
votes
279
views
asked 9 months agolg...
I needed a phase-shifted (relative to the clk_main_a0) clock for my CL, and I implemented that using an MMCME4_ADV in my design. I ran into the well-known sub-optimal placement issues. When I did this...
1
answers
0
votes
187
views
asked 9 months agolg...
Hi,
I have to connect my design with ARM processor and I have to create 2 AFIs with the same design. One is transmitter and another is receiver. But both have to be configured in a different way so...
Accepted AnswerFPGA Development
1
answers
0
votes
223
views
asked 9 months agolg...
Hi,
Getting the following error while implementing my custom logic.
ERROR: [Place 30-678] Failed to do clock region partitioning: Cannot find an available clock routing track for clock net...
Accepted AnswerFPGA Development
3
answers
0
votes
333
views
asked 10 months agolg...
I am trying to do some optimization for network traffic handling by utilizing FGPA acceleration on AWS [F1?].
Per my understanding the F1 service is based on Xilinx Alveo SmartNIC hardware.
So my...
2
answers
1
votes
262
views
asked 10 months agolg...
Hi,
I want to read the signal ** irq_req[15:0]** from the shell.
How to read it..?
Kindly help me.
Thank you
Accepted AnswerFPGA Development
1
answers
0
votes
233
views
asked a year agolg...
Hello,
I'm trying to elaborate with the small shell. First of all, no AMI from AWS with Vivado 2020.2 is available. Probably I can use Vivado 2021.2 to generate IPs, but according to the...
1
answers
0
votes
199
views
asked a year agolg...
Can multiple DCPs be loaded into an AFI and only enable certain DCPs at a time on the fly?
2
answers
0
votes
228
views
asked a year agolg...
Can I have an estimated load time when loading an already generated AFI into a FPGA slot on an F1 instance?
I see that the load time can be decreased through caching and data retention. I have read...
1
answers
0
votes
280
views
asked a year agolg...
Hello,
I am implementing an FPGA IP connected to the AWS shell through AXI interface. The IP performs :
loading data from DDRA,
calculation on these data
storing the result in DDRB
The IP...
1
answers
0
votes
180
views
asked a year agolg...
The goal is to have an FPGA in an F1 instance that can be partially reconfigured on the fly to support a variety of use cases. Could this be done through providing AWS a DCP that in itself partially...
1
answers
0
votes
204
views
asked a year agolg...
Hello I am building my application using AWS F1. But it keeps crashing. I get the following error about pblock overlap. This is internal to F1 shell and CL. I have not created any of these pblocks....
0
answers
0
votes
48
views
asked a year agolg...